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1/23 real-time clock/calendar PCF8563 d e s c r i p t i o n the pcf8 563 is a cmos real-time clock/calendar optim ized for low power consum ption. a program m a ble clock output, interrupt output and voltage-low detector are also provided. all address and data are transferred serially via a two-line bidirectional i 2 c-bus. maxim u m bus speed is 400 kbits/s. the built-in word address register is increm ented autom a tically after each written or read data by te. f e a t u r e s d i p 8 sop8 tssop8 provides y ear, m onth, day , weekday , hour s, m i nutes and seconds based on32.768 khz quartz crystal century flag wide operating supply voltage range: 1.0 to 5.0 v low back-up current; ty pical 0.25 a at v dd = 3.0 v and tam b = 25 c 400 khz two-wire i 2 c-bus interface (at v dd = 1.8 to 5.0 v) program m a ble clock output for peripheral devices: 32.768 khz, 1024 hz, 32 hz and 1 hz alarm and tim er functions voltage-low detector integrated oscillator capacitor internal power-on reset i 2 c-bus slave address: read a3h; write a2h open drain interrupt pin. tiger electronic co.,ltd
PCF8563 2/23 applications mobile telephones portable instrum e nts fax m achines battery powered products block diagram
PCF8563 3/23 pin configura tion sy m b o l p i n d e s c r i p t i o n o s c 1 1 o s c i l l a t o r i n p u t o s c o 2 oscillator o u t p u t i n t 3 interrupt output(ope n-drain; active low) v s s 4 g r o u n d sda 5 serial data i/o clk 6 serial clock input clkout 7 clock output (open-drain) v dd 8 p o s i t i v e supply absolute maximum ra ting ta m b = 2 5 c h a r a c t e r i s t i c s s y m b o l m i n m a x u n i t supply v o ltage v dd - 0 . 5 + 5 . 5 v input v o ltage on inputs scl and sda -0.5 +5.5 v input v o ltage on input osci v i - 0 . 5 v dd + 0 . 5 v output v o ltage on outputs clkout and int v o - 0 . 5 + 5 . 5 v dc input current at any input i i - 1 0 + 1 0 m a dc output current at any output io -10 +10 m a t o tal power dissipation ptot 300 m w operating t e m p erature range t opr -40 +85 s t orage t e m p erature range t s tg -65 +150
PCF8563 4/23 st a t ic electrical characteristics unless otherwise specified v dd = 1.8 to 5.0 v; vss = 0 v; tam b =- 40 to 85 c; f osc = 32.768 khz; quartz rs = 40 k ? ; c l = 8 pf; c h a r a c t e r i s t i c s s y m b o l t e st c o n d i t i o n s min t y p . m a x u n i t supplies i 2 c-bus inactive t a =25 c 1.0*1 5 . 0 v supply voltage i 2 c-bus active f scl =400khz 1.8*1 5 . 0 v supply voltage fo relia ble cl ock/ cale n d a r inform ation v dd t a =25 c v low 5 . 0 v f scl =400khz *2 8 0 0 a f scl =400khz 2 0 0 a f scl =0hz; t a =25 c *2 v dd =5v 2 7 5 5 5 0 n a v dd =3v 2 5 0 5 0 0 n a v dd =2v 2 2 5 4 5 0 n a f scl = 0 h z * 2 v dd =5v 5 0 0 7 5 0 n a v dd =3v 4 0 0 6 5 0 n a supply current clkout disabled (fe=0) i dd1 v dd =2v 4 0 0 6 0 0 n a f scl =0hz; t a =25 c *2 v dd =5v 8 2 5 1 6 0 0 n a v dd =3v 5 5 0 1 0 0 0 n a v dd =2v 4 2 5 8 0 0 n a f scl = 0 h z * 2 v dd =5v 9 5 0 1 7 0 0 n a v dd =3v 6 5 0 1 1 0 0 n a supply current clkout enabled (f clkout =32khz;fe=1) i dd2 v dd =2v 5 0 0 9 0 0 n a inputs low-level input voltage v il v ss 0.3v d d v high-leve l input voltage v ih 0.7v d d v dd v input leakage current i li v i =v dd or v ss - 1 + 1 a input capacitance c i *3 7 pf outputs low-level out put current;pin sda i ol(sda) v ol =0.4v ; v dd =5v - 3 m a
PCF8563 5/23 c h a r a c t e r i s t i c s s y m b o l t e st c o n d i t i o n s min t y p . m a x u n i t l o w - l e v e l o u t p u t current;pin int i ol(int) - 1 m a low-level output current;pin clkout i ol(clko ut) - 1 m a high-level output current;pin clkout i oh(clko ut) v oh =4.6v ; v dd =5v 1 m a output leakage current i lo v o =v dd or v ss - 1 + 1 a v o ltage detector v o ltage-low detection level v low t a =25 c 0.9 1.0 v *1 for reliable oscillator start-up at power-up: v dd (m in)power-up = v dd (m in) + 0.3 v. *2 tim e r source clock = 160 hz; scl and sda = v dd . *3 tested on sam p le basis. dynamic electrical characteristics unless otherwise specified v dd = 1.8 to 5.0 v; vss = 0 v; tam b =- 40 to 85 c; f osc = 32.768 khz; quartz rs = 40 k ? ; c l = 8 pf; c h a r a c t e r i s t i c s s y m b o l t e st c o n d i t i o n s min t y p . m a x u n i t oscillator integrated load capacitance c l(integrat ed) 1 5 2 5 3 5 p f oscillator stability ? f osc /f o sc ? v dd =200m v t a =25 c 210 -7 quartz crystal parameters (f osc =32.768khz ) series resistance r s 4 0 k ? parallel load capacitance c l 1 0 p f t r im m e r capacitance c t 5 2 5 p f clkout output clkout duty factor clkout * 1 5 0 % i 2 c-bus timing characteristics *2 scl clock frequency f scl * 3 4 0 0 k h z st ar t co ndit i o n ho ld tim e t hd;st a 0 . 6 s set-up tim e for a repeated st ar t condition t su;st a 0 . 6 s scl low tim e t low 1 . 3 s scl high tim e t high 0 . 6 s
PCF8563 6/23 c h a r a c t e r i s t i c s s y m b o l t e st c o n d i t i o n s min t y p . m a x u n i t scl and sda rise tim e tr 0.3 s scl and sda fall tim e tf 0.3 s capacitive bus line load cb 400 pf data set-up tim e t su;da t 1 0 0 n s data hold tim e t hd;da t 0 n s set-up tim e for st op condition t su;st o 4 . 0 s t o lerable spike wi dt h on bus t sw 5 0 s *1 unspecified for f clkout = 32.768 khz. *2 all tim ing values are valid within the operating supply voltage range at tam b and referenced to v il and v ih with an input voltage swing of v ss to v dd . *3 i 2 c-bus access tim e between two starts or between a start and a stop condition to this device m u st be less than one second. i2c-bus timing waveforms
PCF8563 7/23 applica t ion circuit method 1: fixed osci capacitor ? by evaluating the average capacitance necessary for the application layout a fixed capacitor can be used. the frequency is best m easured via the 32.768 khz signal available after power-on at the clkout pin. the frequency tolerance depends on the quartz crystal tolerance, the capacitor tolerance and the device-to-device tolerance (on average 510 -6 ). average deviations of 5 m i nutes per year can be easily achieved. method 2: osci trimmer ? the oscillator is tuned to the required accuracy by adjusting a trim m e r capacitor on pin osci and m easur ing the 32.768 khz signal available after power-on at the clkout pin. method 3: osco output ? direct output m easurem ent on pin osco (accounting for test probe capacitance).
PCF8563 8/23 application summary the PCF8563 contains sixteen 8-bit registers with an auto-incrementing address register, an on-chip 32.768 khz oscillator with an integrated capacitor, a frequency divider which provides the source clock for the real-time clock (rtc), a programmable clock output, a timer, an alarm, a voltage-low detector and a 400 khz i 2 c-bus interface. all 16 registers are designed as addressable 8- bit parallel registers although not all bits are implemented. the first two registers (memory address 00h and 01h) are used as control and/or status registers. the memory addresse s 02h through 08h are used as counters for the clock function (seconds up to year counters) . address locations 09h through 0ch contain alarm registers which define the conditions for an alarm. address 0dh controls the clkout output frequency. 0eh and 0fh are the timer control and timer registers, respectively. the seconds, minutes, hours, days, months, year s as well as the minute alarm, hour alarm and day alarm registers are all coded in bcd format. the weekdays and weekday alarm register are not coded in bcd format. when one of the rtc registers is read the contents of all counters are frozen. therefore, faulty reading of the clock/calendar during a carry condition is prevented. alarm function modes by clearing the msb (bit ae = alarm enable) of one or more of the alarm registers, the corresponding alarm condition(s) will be active. in this way an alarm can be generated from once per minute up to once per week. the alarm condition sets the alarm flag, af (bit 3 of control/status 2 register). the asserted af can be used to generate an interrupt (int). bit af can only be cleared by software. timer the 8-bit countdown timer (address 0fh) is controlled by the timer control register (address 0eh). the timer control register sel ects one of 4 source clock frequencies for the timer (4096, 64, 1, or 1/60 hz), and enables/ disables the timer. the timer counts down from a software-loaded 8-bit binary value. at the end of every countdown, the timer sets the timer flag tf. the timer flag tf can only be cl eared by software. the asserted timer flag tf can be used to generate an interrupt (in t). the interrupt may be generated as a pulsed signal every countdown period or as a permanently active signal which follows the condition of tf. ti/tp is used to control this mode selection. when reading the timer, the current countdown value is returned.
PCF8563 9/23 clkout output a program m a ble square wave is available at the clkout pin. operation is controlled by the clkout frequency register (address 0dh) . frequencies of32.768 khz (default), 1024, 32 and 1 hz can be generated for use as a sy stem clock, m i crocontroller clock, input to a charge pum p, or for calibration of the osc illator. clkout is an open-drain output and enabled at power-on. if disabled it becom e s high-im pedance. reset the PCF8563 includes an internal reset circuit which is active whenever the oscillator is stopped. in the reset state the i 2 c-bus logic is initialized and all registers, including the address pointer, are cleared with the ex ception of bits fe, vl, td1, td0, testc a n d a e w h i c h a r e s e t t o l o g i c 1 . v o l t a g e - l o w d e t e c t i o n voltage-low detector and clock monitor the PCF8563 has an on-chip voltage-low detector. when v dd drops below v low the vl bit (voltage low, bit 7 in the seconds register) is set to indicate that reliable clock/calendar inform ation is no longer guaranteed. the vl flag can only be cleared by software. the vl bit is intended to detect the situation when v dd is decreasing slowly for exam ple under battery operation. should v dd reach v low before power is re-asserted then the vl bit will be set. this will indicate that the tim e m a y be corrupted. registers organiz ation table 1 registers overview bit positions labelled as ?- ?are not im plem ented; those labelled with ?0? should alway s be written with logic 0.
PCF8563 10/23 t a ble 2 bcd form atted registers overview bit positions labelled as ?- ?are not im plem ented *1 not coded in bcd contr o l/s tatus 1 r e gister t a ble 3 control/s tatus 1 register bits description(address 00h)
PCF8563 11 / 2 3 contr o l/s tatus 2 r e gister t a ble 4 description of control/s tatus 2 register bits description(address 01h) t a ble 5 int operation(bit ti/tp=1) *1 tf and int becom e active sim u ltaneously . *2 n = loaded countdown tim er value. tim e r stopped when n = 0. t a ble 6 v a lue descriptions for bits af and tf
PCF8563 12/23 seconds,minutes and hours r e gisters t a ble 7 seconds/vl register b its description(address 02h) t a ble 8 minutes register bits description(address 03h) t a ble 9 hours register bits description(address 04h) days,w eekdays,months/century and y e ars r e gisters t a ble 10 day s register bits description(address 05h) t a ble 1 1 w eekday s register bits description(address 06h)
PCF8563 13/23 t a ble 12 w eekday assignm ents t a ble 13 months/century register bits description(address 07h) t a ble 14 month assignm ents t a ble 15 y ears register bits description(address 08h)
PCF8563 14/23 alarm r e gisters when one or m o re of the alarm registers ar e loaded with a valid m i nute, hour, day or weekday and its corresponding ae (alarm enable) bit is a logic 0, then that inform ation will be com p ared with the current m i nute, hour, day and weekday . when all enabled com p arisons first m a tch, the bit af (alarm flag) is set. af will rem a in set until cleared by software. once af has been cleared it will only be set again when the tim e increm ents to m a tch the alarm condition once m o re. alarm registers which have their ae bit set at logic 1 will be ignored. table 16 minute alarm register bits description(address 09h) table 17 hour alarm register b its description(address 0ah) table 18 day alarm register bits description(address 0bh) table 19 weekday alarm register bits description(address 0ch)
PCF8563 15/23 clkout frequency register table 20 clkout frequency register bits description(address 0dh) table 21 clkout frequency selection countdown timer registers the tim e r register is an 8-bit binary countdown tim er. it is enabled and disabled via the tim e r control register bit te. the source clock for the tim er is also selected by the tim e r control register. other tim er properties, e.g. interrupt generation, are controlled via the control/status 2 register. for accurate read back of the countdown value, the i 2 c-bus clock scl m u st be operating at a frequency of at least twice the selected tim er clock. table 22 tim e r control register bits description (address 0eh) t a ble 23 t i m e r source clock frequency selection
PCF8563 16/23 t a ble 24 t i m e r countdown value register bits description(address 0fh) ex t_clk test mode a test m ode is available which allows for on-board testing. in this m ode it is possible to set up test conditions and control the operation of the rtc. the test m ode is entered by setting bit test1 in the control/status1 register. the clkout pin then becom e s an input. the test m ode replaces the internal 64 hz signal with the signal that is applied to the clkout pin. every 64 positive edges applied to clkout will then generate an increm ent of one second. the signal applied to the clkout pin should have a m i nim u m pulse width of 300 ns and a m i nim u m period of 1000 ns. the internal 64 hz clock, now sourced from clkout, is divided down to 1 hz by a 2 6 divide chain called a pre-scal er. the pre-scaler can be set into a known state by using the stop bit. when the stop bit is set, the pre-scaler is reset to 0. stop m u st be cleared before the pre-s caler can operate again. from a stop condition, the first 1 s increm ent will take place afte r32 positive edges on clkout. thereafter, every 64 positive edges will cause a 1 s increm ent. remark: entry into ext_clk test m ode is not sy nchronized to the internal 64 hz clock. when entering the test m ode, no assum p tion as to the state of the pre-scaler can be m a de. operation example 1. enter the ext_clk test m ode; set bit 7 of control/status 1 register (test = 1) 2. set bit 5 of control/status 1 register (stop = 1) 3. clear bit 5 of control/sta tus 1 register (stop = 0) 4. set tim e registers (seconds, minutes, hour s, day s , weekday s , months/century and years) to desired value 5. apply 32 clock pulses to clkout 6. read tim e registers to see the first change 7. apply 64 clock pulses to clkout 8. read tim e registers to see the second change. repeat steps 7 and 8 for additional increm ents. power-on reset (por) override mode the por duration is directly related to the cr y s tal oscillator start-up tim e. due to the long
PCF8563 17/23 start-up tim es experienced by these types of circuits, a m echanism has been built in to disable the por and hence speed up on-board test of the device. the setting of this m ode requires that the i 2 c-bus pins, sda and scl, be toggled in a specific order as shown in figure 5. all tim ing values are required m i nim u m . once the override m ode has been entered, the chip im m e diately stops being reset and norm a l operation starts i.e. entry into the ext_clk test m ode via i 2 c-bus access. the override m ode is cleared by writing a logic 0 to bit testc. re-entry into the override m ode is only possible after testc is set to logi c 1. setting testc to logic 0 during norm a l operation has no effect except to prevent entry into the por override m ode. por override sequence serial interface the serial interface of the PCF8563 is the i 2 c-bus. a detailed description of the i 2 c-bus specification, including applications, is given in the brochure: the i 2 c-bus and how to use it, order no. 9398 393 40011 or i 2 c peripherals data handbook ic12. characteristics of the i 2 c-bus the i 2 c-bus is for bidirectional, two-line com m unication between different ics or m odules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines m u st be connected to a positive supply via a pull-up resi stor. data transfer m a y be initiated only when the bus is not busy . the i 2 c-bus sy stem configuration is shown in figure below. a device generating a m e ssage is a ?transm itter?, a device receiving a m e ssage is the ?receiver?. the device that controls the m e ssage is the ?m aster? and the devices which are controlled by the m a ster are the ?slaves?. i 2 c-bus sy stem configuration
PCF8563 18/23 start and stop conditions both data and clock lines rem a in high when the bus is not busy . a high-to-low transition of the data line, while the clock is high is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p); see figure below. s t a r t a n d s t o p c o n d i t i o n s i 2 c-bus bit transfer one data bit is transferred during each clock pulse. the data on the sda line m u st rem a in stable during the high period of the clock pulse as changes in the data line at this tim e will be interpreted as a control signal; see figure below.. b i t t r a n s f e r o n t h e i 2 c-bus acknowledge the num ber of data by tes transferred between the start and stop conditions from transm itter to receiver is unlim ited. each by te of eight bits is followed by an acknowledge bit. the acknowledge bit is a high level signal put on the bus by the transm itter during which tim e the m a ster generates an extra acknowledge related clock pulse. a slave receiver which is addressed m u st ge nerate an acknowledge after the reception of each by te. also a m a ster receiver m u st generate an acknowledge after the reception of each byte that has been clocked out of the slave transm itter.
PCF8563 19/23 the device that acknowledges m u st pull down the sda line during the acknowledge clock pulse, so that the sda line is stable lo w during the high period of the acknowledge related clock pulse (set-up and hold tim es m u st be taken into consideration). a m a ster receiver m u st signal an end of data to the transm itter by not generating an acknowledge on the last by te that has been clocked out of the slave. in this event the transm itter m u st leave the data line high to enable the m a ster to generate a stop condition. acknowledge on the i 2 c-bus i 2 c-bus protocol addressing: before any data is transm itted on the i2c-bus, the device which should respond is addressed first. the addressing is alway s carried out with the first by te transm itted after the start procedure. the PCF8563 acts as a slave receiver or slave tr ansmitter. therefore the clock signal scl is only an input signal, but the data signal sda is a bidirectional line. the PCF8563 slave address is shown in figure below. slave address clock/calendar read/write cycles: the i 2 c-bus configuration for the different PCF8563 read and write cy cles are shown in figure 11, 12 a nd 13. the word address is a four bit value that defines which register is to be accessed next. the upper four bits of the word address are not used.
PCF8563 20/23 master transm its to slave receiver(write m ode) m a s t e r r e a d s a f f e r s e t t i n g w o rd address(write word address;read data) master reads slave im m e diately after first byte (read m ode)
PCF8563 21/23 characteristics cur ves
PCF8563p / PCF8563t 22/23 outline dra wing d i p 8 unit:m m s o p 8 unit:m m
PCF8563ts 23/23 t s s o p 8 unit:m m

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